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| CYV15G0404RB Independent Clock Quad HOTLink IITM Deserializing Reclocker Features * Second-generation HOTLink(R) technology * Compliant to SMPTE 292M and SMPTE 259M video standards * Quad channel video reclocking deserializer -- 195 to 1500 Mbps serial data signaling rate -- Simultaneous operation at different signaling rates * Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock * Supports half-rate and full-rate clocking * Internal phase-locked loops (PLLs) with no external PLL components * Selectable differential PECL-compatible serial inputs * * * * -- Internal DC restoration Synchronous LVTTL parallel interface JTAG boundary scan Built-In Self-Test (BIST) for at-speed link testing Link Quality Indicator -- Analog signal detect * * * * * -- Digital signal detect Low-power: 3W @ 3.3V typical Single 3.3V supply Thermally enhanced BGA Pb-Free package option available 0.25 BiCMOS technology and SMPTE 259 video applications. It supports signaling rates in the range of 195 to 1500 Mbps for each serial link. The four channels are independent and can simultaneously operate at different rates. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1, "HOTLink IITM System Connections," on page 2 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404RB Reclocking Deserializer and CYV15G0403TB Serializer chips. The CYV15G0404RB is SMPTE-259M and SMPTE-292M compliant according to SMPTE EG34-1999 Pathological Test Requirements. As a second generation HOTLink device, the CYV15G0404RB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. Each channel of the CYV15G0404RB Quad HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The device reclocks and retransmits recovered bit-stream through the reclocker serial outputs. It also deserializes the recovered serial data and presents it to the destination host system. Each channel contains an independent BIST pattern checker. This BIST hardware enables at speed testing of the high-speed serial data paths in each receive section of this device, each transmit section of a connected HOTLink II device, and across the interconnecting links. The CYV15G0404RB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers, switchers, format converters, SDI monitors, and camera control units. Functional Description The CYV15G0404RB Independent Clock Quad HOTLink IITM Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer over a variety of high speed serial links including SMPTE 292 Cypress Semiconductor Corporation Document #: 38-02102 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised February 16, 2007 [+] Feedback CYV15G0404RB Figure 1. HOTLink IITM System Connections Reclocked Outputs 10 10 10 Independent Channel CYV15G0403TB Serializer Serial Links Independent Channel CYV15G0404RB Reclocking Deserializer 10 10 10 10 Reclocked Outputs CYV15G0404RB Deserializing Reclocker Logic Block Diagram TRGCLKA TRGCLKB TRGCLKC Video Coprocessor x10 x10 x10 x10 Deserializer Deserializer Deserializer Deserializer Reclocker RX Reclocker RX Reclocker RX Reclocker RX ROUTC1 ROUTC2 ROUTD1 ROUTD2 ROUTB1 ROUTB2 ROUTA1 ROUTA2 INC1 INC2 Document #: 38-02102 Rev. *C Page 2 of 27 IND1 IND2 INA1 INA2 INB1 INB2 TRGCLKD [+] Feedback RXDA[9:0] RXDB[9:0] RXDC[9:0] RXDD[9:0] Video Coprocessor 10 CYV15G0404RB Reclocking Deserializer Path Block Diagram TRGRATEA TRGCLKA SDASEL[2..1]A[1:0] LDTDEN = Internal Signal RESET TRST x2 JTAG Boundary Scan Controller TMS TCLK TDI TDO BIST LFSR Output Register INSELA INA1+ INA1- INA2+ INA2- ULCA SPDSELA RXPLLPDA Shifter Receive Signal Monitor Clock & Data Recovery PLL LFIA 10 10 10 RXDA[9:0] BISTSTA /2 RXBISTA[1:0] RXRATEA RXCLKA+ RXCLKA- Recovered Character Clock Recovered Serial Data ROE[2..1]A Reclocker Output PLL Clock Multiplier A RECLKOA REPDOA TRGRATEB TRGCLKB SDASEL[2..1]B[1:0] LDTDEN Character-Rate Clock A Register ROE[2..1]A ROUTA1+ ROUTA1- ROUTA2+ ROUTA2- x2 BIST LFSR Output Register INSELB INB1+ INB1- INB2+ INB2- ULCB SPDSELB RXPLLPDB Shifter Receive Signal Monitor Clock & Data Recovery PLL LFIB 10 10 10 RXDB[9:0] BISTSTB /2 RXBISTB[1:0] RXRATEB RXCLKB+ RXCLKB- Recovered Character Clock Recovered Serial Data ROE[2..1]B Reclocker Output PLL Clock Multiplier B RECLKOB REPDOB Character-Rate Clock B Register ROE[2..1]B ROUTB1+ ROUTB1- ROUTB2+ ROUTB2- Document #: 38-02102 Rev. *C Page 3 of 27 [+] Feedback CYV15G0404RB Reclocking Deserializer Path Block Diagram (continued) TRGRATEC TRGCLKC SDASEL[2..1]C[1:0] LDTDEN = Internal Signal x2 BIST LFSR Output Register INSELC INC1+ INC1- INC2+ INC2- ULCC SPDSELC RXPLLPDC Shifter Receive Signal Monitor Clock & Data Recovery PLL LFIC 10 10 10 RXDC[9:0] BISTSTC /2 RXBISTC[1:0] RXRATEC RXCLKC+ RXCLKC- Recovered Character Clock Recovered Serial Data ROE[2..1]C Reclocker Output PLL Clock Multiplier C RECLKOC REPDOC TRGRATED TRGCLKD SDASEL[2..1]D[1:0] LDTDEN Character-Rate Clock C Register ROE[2..1]C ROUTC1+ ROUTC1- ROUTC2+ ROUTC2- x2 BIST LFSR Output Register INSELD IND1+ IND1- IND2+ IND2- ULCD SPDSELD RXPLLPDD Shifter Receive Signal Monitor Clock & Data Recovery PLL LFID 10 10 10 RXDD[9:0] BISTSTD /2 RXBISTD[1:0] RXRATED RXCLKD+ RXCLKD- Recovered Character Clock Recovered Serial Data ROE[2..1]D Reclocker Output PLL Clock Multiplier D RECLKOD REPDOD Character-Rate Clock D Register ROE[2..1]D ROUTD1+ ROUTD1- ROUTD2+ ROUTD2- Document #: 38-02102 Rev. *C Page 4 of 27 [+] Feedback CYV15G0404RB Device Configuration and Control Block Diagram RXBIST[A..D] RXRATE[A..D] SDASEL[A..D][1:0] RXPLLPD[A..D] ROE[2..1][A..D] GLEN[11..0] FGLEN[2..0] = Internal Signal WREN ADDR[3:0] DATA[7:0] Device Configuration and Control Interface Document #: 38-02102 Rev. *C Page 5 of 27 [+] Feedback CYV15G0404RB Pin Configuration (Top View)[1] 1 A B C D E F G H J K L M N P R T U V W Y IN C1- IN C1+ TDI 2 ROUT C1- ROUT C1+ TMS 3 IN C2- IN C2+ 4 ROUT C2- ROUT C2+ 5 VCC VCC VCC VCC 6 IN D1- IN D1+ ULCD 7 ROUT D1- ROUT D1+ ULCC 8 GND 9 IN D2- IN D2+ DATA [7] DATA [6] 10 ROUT D2- ROUT D2+ DATA [5] DATA [4] 11 IN A1- IN A1+ DATA [3] DATA [2] 12 ROUT A1- ROUT A1+ DATA [1] DATA [0] 13 GND 14 IN A2- IN A2+ 15 ROUT A2- ROUT A2+ SPD SELD ULCB 16 VCC VCC VCC VCC 17 IN B1- IN B1+ LDTD EN 18 ROUT B1- ROUT B1+ TRST 19 IN B2- IN B2+ 20 ROUT B2- ROUT B2+ TDO GND GND INSELC INSELB GND GND VCC GND GND TCLK RESET INSELD INSELA ULCA SPD SELC GND GND NC VCC VCC SCAN TMEN3 EN2 VCC VCC VCC VCC VCC VCC VCC RX DC[8] RX DC[9] WREN VCC GND VCC GND VCC SPD SELB RX DB[0] RE CLKOB SPD SELA RX DB[1] RX DB[3] GND NC GND GND GND GND GND GND GND GND GND GND GND GND BIST STB RX DB[2] RX DB[7] RX DB[4] RX DC[4] TRG CLKC- GND GND RX DB[5] RX DB[6] RX DB[9] LFIB RX DC[5] TRG CLKC+ LFIC GND RX DB[8] RX RX CLKB+ CLKB- GND RX DC[6] RX DC[7] VCC GND RE PDOC TRG TRG CLKB+ CLKB- RE PDOB GND GND GND GND GND GND GND GND RX DC[3] BIST STC RX DC[2] RX DC[1] RX DC[0] GND GND GND GND RE RX RX CLKOC CLKC+ CLKC- VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RX DD[4] RX DD[3] GND GND ADDR TRG [0] CLKD- GND GND GND VCC VCC RX DA[4] VCC BIST STA RX DA[0] VCC VCC VCC RX DD[8] VCC RX DD[5] RX DD[1] GND BIST STD ADDR TRG RE [2] CLKD+ CLKOA GND GND VCC VCC RX DA[9] RX DA[5] RX DA[2] RX DA[1] VCC VCC LFID RX CLKD- VCC RX DD[6] RX DD[0] GND ADDR [3] ADDR [1] RX CLKA+ RE PDOA GND GND VCC VCC LFIA TRG CLKA+ RX DA[6] RX DA[3] VCC VCC RX DD[9] RX CLKD+ VCC RX DD[7] RX DD[2] GND RE CLKOD NC GND RX CLKA- GND GND VCC VCC RE TRG PDOD CLKA- RX DA[8] RX DA[7] Note 1. NC = Do not connect. Document #: 38-02102 Rev. *C Page 6 of 27 [+] Feedback CYV15G0404RB Pin Configuration (Bottom View)[1] 20 A B C D E F G H J K L M N P R T U V W Y ROUT B2- 19 IN B2- 18 ROUT B1- 17 IN B1- 16 VCC 15 ROUT A2- 14 IN A2- 13 GND 12 ROUT A1- 11 IN A1- 10 ROUT D2- 9 IN D2- 8 GND 7 ROUT D1- 6 IN D1- 5 VCC 4 ROUT C2- 3 IN C2- 2 ROUT C1- 1 IN C1- ROUT B2+ IN B2+ ROUT B1+ IN B1+ VCC ROUT A2+ IN A2+ GND ROUT A1+ IN A1+ ROUT D2+ IN D2+ GND ROUT D1+ IN D1+ VCC ROUT C2+ IN C2+ ROUT C1+ IN C1+ TDO GND TRST LDTD EN VCC SPD SELD VCC GND DATA [1] DATA [3] DATA [5] DATA [7] GND ULCC ULCD VCC INSELB INSELC TMS TDI TMEN3 SCAN EN2 VCC NC VCC ULCB GND GND DATA [0] DATA [2] DATA [4] DATA [6] GND SPD SELC ULCA VCC INSELA INSELD RESET TCLK VCC VCC VCC VCC VCC VCC VCC VCC RX DB[1] RE CLKOB RX DB[0] VCC VCC VCC RX DC[9] RX DC[8] RX DB[3] SPD SELA NC SPD SELB GND GND WREN GND GND GND GND GND GND GND GND GND RX DB[4] RX DB[7] RX DB[2] BIST STB GND GND GND GND LFIB RX DB[9] RX DB[6] RX DB[5] GND GND TRG CLKC- RX DC[4] GND RX RX CLKB- CLKB+ RX DB[8] GND LFIC TRG CLKC+ RX DC[5] GND RE PDOB TRG TRG CLKB- CLKB+ RE PDOC VCC RX DC[7] RX DC[6] GND GND GND GND GND GND GND GND GND GND GND GND RX DC[0] RX DC[1] RX DC[2] RX DC[3] VCC VCC VCC VCC RX RX RE CLKC- CLKC+ CLKOC BIST STC VCC VCC VCC VCC VCC VCC VCC VCC RX DA[0] BIST STA VCC RX DA[4] VCC VCC GND GND GND TRG ADDR CLKD- [0] GND GND RX DD[3] RX DD[4] VCC VCC VCC VCC VCC RX DA[1] RX DA[2] RX DA[5] RX DA[9] VCC VCC GND GND RE TRG ADDR CLKOA CLKD+ [2] BIST STD GND RX DD[1] RX DD[5] VCC RX DD[8] VCC VCC VCC RX DA[3] RX DA[6] TRG CLKA+ LFIA VCC VCC GND GND RE PDOA RX CLKA+ ADDR [1] ADDR [3] GND RX DD[0] RX DD[6] VCC RX CLKD- LFID VCC VCC RX DA[7] RX DA[8] TRG RE CLKA- PDOD VCC VCC GND GND RX CLKA- GND NC RE CLKOD GND RX DD[2] RX DD[7] VCC RX CLKD+ RX DD[9] VCC VCC Document #: 38-02102 Rev. *C Page 7 of 27 [+] Feedback CYV15G0404RB Pin Definitions CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name RXDA[9:0] RXDB[9:0] RXDC[9:0] RXDD[9:0] IO Characteristics LVTTL Output, synchronous to the RXCLK output Signal Description Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the receive interface clock. If RXCLKx is a full-rate clock, the RXCLKx clock outputs are complementary clocks operating at the character rate. The RXDx[9:0] outputs for the associated receive channels follow the rising edge of RXCLKx+ or the falling edge of RXCLKx-. If RXCLKx is a half-rate clock, the RXCLKx clock outputs are complementary clocks operating at half the character rate. The RXDx[9:0] outputs for the associated receive channels follow both the falling and rising edges of the associated RXCLKx clock outputs. When BIST is enabled on the receive channel, the RXDx[1:0] and BISTSTx outputs present the BIST status. See Table 5, "Receive BIST Status Bits," on page 17 for each status that the BIST state machine reports. Also, while BIST is enabled, ignore the RXDx[9:2] outputs. BISTSTA BISTSTB BISTSTC BISTSTD REPDOA REPDOB REPDOC REPDOD TRGCLKA TRGCLKB TRGCLKC TRGCLKD LVTTL Output, synchronous to the RXCLKx output Asynchronous to reclocker output channel enable / disable BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0]) displays the status of the BIST reception. See Table 5, "Receive BIST Status Bits," on page 17 for the BIST status for each combination of BISTSTx and RXDx[1:0]. When RXBISTx[1:0] 10, ignore BISTSTx. Reclocker Powered Down Status Output. REPDOx asserts HIGH when the associated channel's reclocker output logic powers down. This occurs when disabling ROE2x and ROE1x by setting ROE2x = 0 and ROE1x = 0. Receive Path Data and Status Signals Receive Path Clock Signals Differential LVPECL or CDR PLL Training Clock. The frequency detector (Range Controller) of the single-ended associated receive PLL uses the TRGCLKx clock inputs as the reference source LVTTL input clock to reduce PLL acquisition time. In the presence of valid serial data, the recovered clock output of the receive CDR PLL (RXCLKx) has no frequency or phase relationship with TRGCLKx. When a single-ended LVCMOS or LVTTL clock source drives the clock, connect the clock source to either the true or complement TRGCLKx input, and leave the alternate TRGCLKx input open (floating). When an LVPECL clock source drives it, the clock must be a differential clock, using both inputs. RXCLKA RXCLKB RXCLKC RXCLKD RECLKOA RECLKOB RECLKOC RECLKOD LVTTL Output Clock Receive Clock Output. RXCLKx is the receive interface clock that controls timing of the RXDx[9:0] parallel outputs. These true and complement clocks control timing of data output transfers. These clocks output continuously at either the half-character rate (1/20 the serial bit-rate) or character rate (1/10 the serial bit-rate) of the data being received, as selected by RXRATEx. Reclocker Clock Output. The associated reclocker output PLL synthesizes the RECLKOx output clock, which operates synchronous to the internal recovered character clock. RECLKOx operates at either the same frequency as RXCLKx (RXRATEx = 0), or at twice the frequency of RXCLKx (RXRATEx = 1). The reclocker clock outputs have no fixed phase relationship to RXCLKx. Asynchronous Device Reset. RESET initializes all state machines, counters, and configuration latches in the device to a known state. RESET must assert LOW for a minimum pulse width. When the reset is removed, all state machines, counters and configuration latches are at an initial state. According to the JTAG specifications, the device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has to be reset separately. Refer to "JTAG Support" on page 17 for the methods to reset the JTAG state machine. See Table 3, "Device Configuration and Control Latch Descriptions," on page 14 for the initialize values of the device configuration latches. LVTTL Output Device Control Signals RESET LVTTL Input, asynchronous, internal pull up Document #: 38-02102 Rev. *C Page 8 of 27 [+] Feedback CYV15G0404RB Pin Definitions (continued) CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name LDTDEN IO Characteristics LVTTL Input, internal pull up Signal Description Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level Detector, Range Controller, and Transition Density Detector are all enabled to determine if the RXPLL tracks TRGCLKx or the selected input serial data stream. If the Signal Level Detector, Range Controller, or Transition Density Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks to TRGCLKx until they become valid. The SDASEL[A..D][1:0] inputs configure the trip level of the Signal Level Detector. The Transition Density Detector limit is one transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range Controller determines if the RXPLL tracks TRGCLKx or the selected input serial data stream. Set LDTDEN = HIGH. Use Local Clock. When ULCx is LOW, the RXPLL locks to TRGCLKx instead of the received serial data stream. While ULCx is LOW, the LFIx for the associated channel is LOW, indicating a link fault. When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on the input data streams. This function is used in applications that need a stable RXCLKx. When valid data transitions are absent for a long time, or the high-gain differential serial inputs (INx) are left floating, the RXCLKx outputs may briefly be different from TRGCLKx. Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range of each channel's receive PLL. LOW = 195-400 MBd MID = 400-800 MBd HIGH = 800-1500 MBd. Receive Input Selector. The INSELx input determines which external serial bit stream passes to the receiver's Clock and Data Recovery circuit. When INSELx is HIGH, the Primary Differential Serial Data Input, INx1, is the associated receive channel. When INSELx is LOW, the Secondary Differential Serial Data Input, INx2, is the associated receive channel. Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the logical OR of six internal conditions. LFIx asserts LOW when any of the following conditions is true: * Received serial data rate is outside expected range * Analog amplitude is below expected levels * Transition density is lower than expected * Receive is channel disabled * ULCx is LOW * TRGCLKx is absent. Control Write Enable. The WREN input writes the values of the DATA[7:0] bus into the latch specified by the address location on the ADDR[3:0] bus.[3] Control Addressing Bus. The ADDR[3:0] bus is the input address bus that configures the device. The WREN input writes the values of the DATA[7:0] bus into the latch specified by the address location on the ADDR[3:0] bus.[3] Table 3, "Device Configuration and Control Latch Descriptions," on page 14 lists the configuration latches within the device, and the initialization value of the latches when RESET is asserted. Table 4, "Device Control Latch Configuration Table," on page 16 shows how the latches are mapped in the device. ULCA ULCB ULCC ULCD LVTTL Input, internal pull up SPDSELA SPDSELB SPDSELC SPDSELD 3-Level Select[2] static control input INSELA INSELB INSELC INSELD LFIA LFIB LFIC LFID LVTTL Input, asynchronous LVTTL Output, asynchronous Device Configuration and Control Bus Signals WREN LVTTL input, asynchronous, internal pull up LVTTL input asynchronous, internal pull up ADDR[3:0] Notes 2. Use 3-Level Select inputs for static configuration. These are ternary inputs that use logic levels of LOW, MID, and HIGH. To implement the LOW level, connect directly to VSS (ground). To implement the HIGH level, connect directly to VCC (power). To implement the MID level, do not connect the input (leave floating), which allows it to self bias to the proper level. 3. See "Device Configuration and Control Interface" on page 13 for detailed information about the operation of the Configuration Interface. Document #: 38-02102 Rev. *C Page 9 of 27 [+] Feedback CYV15G0404RB Pin Definitions (continued) CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name DATA[7:0] IO Characteristics LVTTL input asynchronous, internal pull-up Signal Description Control Data Bus. The DATA[7:0] bus is the input data bus that configures the device. The WREN input writes the values of the DATA[7:0] bus into the latch specified by address location on the ADDR[3:0] bus.[3] Table 3, "Device Configuration and Control Latch Descriptions," on page 14 lists the configuration latches within the device, and the initialization value of the latches when RESET is asserted. Table 4, "Device Control Latch Configuration Table," on page 16 shows the way the latches are mapped in the device. Receive Clock Rate Select. Signal Detect Amplitude Select. Receive Channel Power Control. Receive BIST Disabled. Reclocker Differential Serial Output Driver 2 Enable. Reclocker Differential Serial Output Driver 1 Enable. Global Latch Enable. Force Global Latch Enable. Factory Test 2. The SCANEN2 input is for factory testing only. Leave this input as a NO CONNECT, or GND only. Factory Test 3. The TMEN3 input is for factory testing only. Leave this input as a NO CONNECT, or GND only. Primary Differential Serial Data Output. The ROUTx1 PECL-compatible CML outputs (+3.3V referenced) can drive terminated transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connections. Secondary Differential Serial Data Output. The ROUTx2 PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be AC coupled for PECL-compatible connections. Primary Differential Serial Data Input. The INx1 input accepts the serial data stream for deserialization. The INx1 serial stream passes to the receive CDR circuit to extract the data content when INSELx = HIGH. Secondary Differential Serial Data Input. The INx2 input accepts the serial data stream for deserialization. The INx2 serial stream passes to the receiver CDR circuit to extract the data content when INSELx = LOW. Internal Device Configuration Latches RXRATE[A..D] Internal Latch[4] [4] SDASEL[2..1][A..D] Internal Latch [1:0] RXPLLPD[A..D] RXBIST[A..D][1:0] ROE2[A..D] ROE1[A..D] GLEN[11..0] FGLEN[2..0] SCANEN2 TMEN3 Analog I/O ROUTA1 ROUTB1 ROUTC1 ROUTD1 ROUTA2 ROUTB2 ROUTC2 ROUTD2 INA1 INB1 INC1 IND1 INA2 INB2 INC2 IND2 JTAG Interface TMS TCLK Internal Latch Internal Latch[4] [4] [4] [4] Internal Latch Internal Latch Internal Latch Internal Latch[4] [4] Factory Test Modes LVTTL input, internal pull down LVTTL input, internal pull down CML Differential Output CML Differential Output Differential Input Differential Input LVTTL Input, internal pull up LVTTL Input, internal pull down Test Mode Select. Controls access to the JTAG Test Modes. If TMS is HIGH for >5 TCLK cycles, the JTAG test controller resets. JTAG Test Clock. Note 4. See Device Configuration and Control Interface for detailed information on the internal latches. Document #: 38-02102 Rev. *C Page 10 of 27 [+] Feedback CYV15G0404RB Pin Definitions (continued) CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name TDO TDI TRST Power VCC GND +3.3V Power. Signal and Power Ground for all internal circuits. All of these conditions must be valid for the Signal Detect block to indicate a valid signal is present. This status is presented on the LFIx (Link Fault Indicator) output associated with each receive channel, which changes synchronous to the receive interface clock. Analog Amplitude While most signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with highly attenuated signals, or in high noise environments. The SDASELx latch sets the analog amplitude level detection via the device configuration interface. The SDASELx latch sets the trip point for the detection of a valid signal at one of three levels, as listed in Table 1. This control input affects the analog monitors for all receive channels. The Analog Signal Detect monitors are active for the Line Receiver, as selected by the associated INSELx input. Table 1. Analog Amplitude Detect Valid Signal Levels[5] SDASEL Typical Signal with Peak Amplitudes Above 00 01 10 11 Analog Signal Detector is disabled 140 mV p-p differential 280 mV p-p differential 420 mV p-p differential IO Characteristics 3-State LVTTL Output LVTTL Input, internal pull up LVTTL Input, internal pull up Signal Description Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected. Test Data In. JTAG data input port. JTAG reset signal. When asserted (LOW), this input asynchronously resets the JTAG test access port controller. CYV15G0404RB HOTLink II Operation The CYV15G0404RB is a highly configurable, independent clocking, quad-channel reclocking deserializer that supports reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple destinations. This device supports four 10-bit channels. CYV15G0404RB Receive Data Path Serial Line Receivers Two differential Line Receivers, INx1 and INx2, are available on each channel to accept serial data streams. The associated INSELx input selects the active Serial Line Receiver on a channel. The Serial Line Receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmission line attenuation greater than 16 dB. For normal operation, these inputs must receive a signal of at least VIDIFF > 100 mV, or 200 mV peak-to-peak differential. Each Line Receiver can be DC or AC coupled to +3.3V powered fiber-optic interface modules (any ECL/PECL family, not limited to 100K PECL) or AC coupled to +5V powered optical modules. The common mode tolerance of these line receivers accommodates a wide range of signal termination voltages. Each receiver provides internal DC restoration, to the center of the receiver's common mode range, for AC coupled signals. Signal Detect/Link Fault Each selected Line Receiver (that is, that routed to the clock and data recovery PLL) is simultaneously monitored for * Analog amplitude above amplitude level selected by SDASELx * Transition density above the specified limit * Range controls reporting the received data stream inside normal frequency range (1500 ppm[21]) * Receive channel enabled * Reference clock present * ULCx not asserted. Transition Density The Transition Detection logic checks for the absence of transitions spanning greater than six transmission characters (60 bits). If there are no transitions in the data received, the Detection logic for that channel asserts LFIx. Range Controls The CDR circuit includes logic to monitor the frequency of the PLL Voltage Controlled Oscillator (VCO) samples the incoming data stream. This logic ensures that the VCO Note 5. The peak amplitudes listed in this table are for typical waveforms that generally have 3-4 transitions for every ten bits. In a worst case environment the signals may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mV. Document #: 38-02102 Rev. *C Page 11 of 27 [+] Feedback CYV15G0404RB operates at, or near the rate of the incoming data stream for two primary cases: * When the incoming data stream resumes after a time in which it was "missing." * When the incoming data stream is outside the acceptable signaling rate range. To perform this function, periodically compare the frequency of the RXPLL VCO to the frequency of the TRGCLKx input. If the VCO is running at a frequency beyond 1500 ppm[21] as defined by the TRGCLKx frequency, it is periodically forced to the correct frequency (as defined by TRGCLKx, SPDSELx, and TRGRATEx) and then released in an attempt to lock to the input data stream. Calculate the sampling and relock period of the Range Control as follows: RANGE_CONTROL_SAMPLING_PERIOD = (RECOVERED BYTE CLOCK PERIOD) * (4096). During the time that the Range Control forces the RXPLL VCO to track TRGCLKx, the LFIx output is asserted LOW. After a valid serial data stream is applied, it may take up to one RANGE CONTROL SAMPLING PERIOD before the PLL locks to the input data stream, after which LFIx is HIGH. Table 2 lists the operating serial signaling rate and allowable range of TRGCLK frequencies. Table 2. Operating Speed Settings SPDSELx LOW MID (Open) HIGH TRGRATEx 1 0 1 0 1 0 Receive Channel Enabled The CYV15G0404RB contains four receive channels that it can independently enable and disable. Each channel are enabled or disabled separately through the RXPLLPDx input latch as controlled by the device configuration interface. RXPLLPDx latch = 0 disables the associated PLL and analog circuitry of the channel. Any disabled channel indicates a constant link fault condition on the LFIx output. RXPLLPDx = 1 enables the associated PLL and receive channel to receive a serial stream. Note When a disabled receive channel is reenabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. Clock/Data Recovery A separate CDR block within each receive channel performs the extraction of a bit rate clock and recovery of bits from each received serial stream. An integrated PLL that tracks the frequency of the transitions in the incoming bit stream and aligns the phase of the internal bit rate clock to the transitions TRGCLKx Frequency (MHz) Reserved 19.5-40 20-40 40-80 40-75 80-150 800-1500 400-800 Signaling Rate (Mbps) 195-400 in the selected serial data stream performs the clock extraction function. Each CDR accepts a character-rate (bit-rate / 10) or half-character-rate (bit-rate / 20) training clock from the associated TRGCLKx input. This TRGCLKx input is used to * Ensure that the VCO (within the CDR) is operating at the correct frequency (rather than a harmonic of the bit rate) * Reduce PLL acquisition time * Limit unlocked frequency excursions of the CDR VCO when there is no input data present at the selected Serial Line Receiver. Regardless of the type of signal present, the CDR attempts to recover a data stream from it. If the signaling rate of the recovered data stream is outside the limits set by the range control monitors, the CDR tracks TRGCLKx instead of the data stream. Once the CDR output (RXCLK) frequency returns close to TRGCLKx frequency, the CDR input switches back to the input data stream. If no data is present at the selected line receiver, this switching behavior may cause brief RXCLK frequency excursions from TRGCLKx. However, the LFIx output indicates the validity of the input data stream. The frequency of TRGCLKx must be within 1500 ppm[21] of the frequency of the clock that drives the reference clock input of the remote transmitter, to ensure a lock to the incoming data stream. This large ppm tolerance allows the CDR PLL to reliably receive a 1.485 or 1.485/1.001 Gbps SMPTE HD-SDI data stream with a constant TRGCLK frequency. For systems using multiple or redundant connections, use the LFIx output to select an alternate data stream. When the device detects an LFIx indication, external logic toggles selection of the associated INx1 and INx2 input through the associated INSELx input. When a port switch takes place, the receive PLL for that channel reacquires the new serial stream. Reclocker Each receive channel performs a reclocker function on the incoming serial data. To do this, the Clock and Data Recovery PLL first recovers the clock from the data. The recovered clock retimes the data and then passes it to an output register. It also passes the recovered character clock from the receive PLL to the reclocker output PLL, which generates the bit clock that clocks the retimed data into the output register. This data stream is then transmitted through the differential serial outputs. Reclocker Serial Output Drivers The serial output interface drivers use differential Current Mode Logic (CML) drivers to provide source-matched drivers for 50 transmission lines. These drivers accept data from the reclocker output register in the reclocker channel. These drivers have signal swings equivalent to that of standard PECL drivers, and can drive AC coupled optical modules or transmission lines. Reclocker Output Channels Enabled Each driver can be enabled or disabled separately via the device configuration interface. When a driver is disabled using the configuration interface, it internally powers down to reduce device power. If both Page 12 of 27 Document #: 38-02102 Rev. *C [+] Feedback CYV15G0404RB reclocker serial drivers for a channel are in this disabled state, the associated internal reclocker logic also powers down. The deserialization logic and parallel outputs remain enabled. A device reset (RESET sampled LOW) disables all output drivers. Note When the disabled reclocker function (that is, both outputs disabled) is reenabled, the data on the reclocker serial outputs may not meet all timing specifications for up to 250 s. Output Bus Each receive channel presents a 10-bit data signal (and a BIST status signal when RXBISTx[1:0] = 10). Receive BIST Operation Each receiver channel contains an internal pattern checker that is used to validate both device and link operation. These pattern checkers are enabled by the associated RXBISTx[1:0] latch through the device configuration interface. When enabled, a register in the associated receive channel becomes a signature pattern generator and checker by logically converting to a Linear Feedback Shift Register (LFSR). This LFSR generates a 511-character sequence. This provides a predictable, yet pseudorandom, sequence that can be matched to an identical LFSR in the attached Transmitter(s). When synchronized with the received data stream, the associated Receiver checks each character from the deserializer with each character generated by the LFSR and indicates compare errors and BIST status at the RXDx[1:0] and BISTSTx bits of the Output Register. The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates 010b or 100b for one character period per BIST loop to indicate loop completion. Use this status to check test pattern progress. Table 5, "Receive BIST Status Bits," on page 17 lists the specific status reported by the BIST state machine. The receive status outputs report these same codes. If the number of invalid characters received exceeds the number of valid characters by 16, the receive BIST state machine aborts the compare operations and resets the LFSR to look for the start of the BIST sequence again. A device reset (RESET sampled LOW) presets the BIST Enable Latches to disable BIST on all channels. BIST Status State Machine When a receive path is enabled to look for and compare the received data stream with the BIST pattern, the {BISTSTx, RXDx[0], RXDx[1]} bits identify the present state of the BIST compare operation. The BIST state machine has multiple states, as shown in Figure 2, "Receive BIST State Machine," on page 18 and Table 5, "Receive BIST Status Bits," on page 17. When the receive PLL detects an out-of-lock condition, it forces the BIST state to the Start-of-BIST state, regardless of the present state of the BIST state machine. If the number of detected errors ever exceeds the number of valid matches by greater than 16, the state machine is forced to the WAIT_FOR_BIST state, where it monitors the receive path for the first character of the next BIST sequence. Power Control The CYV15G0404RB supports user control of the powered up or down state of each transmit and receive channel. The RXPLLPDx latch controls the receive channels through the device configuration interface. RXPLLPDx = 0 disables the associated PLL and analog circuitry of the channel. The OE1x and the OE2x latches control the transmit channels via the device configuration interface. The ROE1x and the ROE2x latches control the reclocker function through the device configuration interface. When the configuration interface disables a driver, the driver internally powers down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel also powers down. The reclocker serial drivers being disabled in turn disables the reclocker function, but the deserialization logic and parallel outputs remain enabled. Device Reset State Assertion of RESET resets all state machines, counters, and configuration latches in the device to a reset state. Additionally, the JTAG controller must be reset for valid operation (even if not performing JTAG testing). See "JTAG Support" on page 17 for JTAG state machine initialization. See Table 3, "Device Configuration and Control Latch Descriptions," on page 14 for the initialize values of the configuration latches. Following a device reset, enable the receive channels used for normal operation. Do this by sequencing the appropriate values on the device configuration interface.[3] Device Configuration and Control Interface Configure the CYV15G0404RB through the configuration interface. The configuration interface enables the device to be configured globally or enables each channel to be configured independently. Table 3, "Device Configuration and Control Latch Descriptions," on page 14 lists the configuration latches within the device, including the initialization value of the latches on the assertion of RESET. Table 4, "Device Control Latch Configuration Table," on page 16 shows how the latches are mapped in the device. Each row in Table 4 maps to an 8-bit latch bank. There are 16 such write only latch banks. When WREN = 0, the logic value in the DATA[7:0] latches to the latch bank specified by the values in ADDR[3:0]. The second column of Table 4 specifies the channels associated with the corresponding latch bank. For example, the first three latch banks (0, 1, and 2) consist of configuration bits for channel A. Latch banks 12, 13, and 14 consist of Global configuration bits, and the last latch bank (15) is the Mask latch bank, which can be configured to perform bit-by-bit configuration. Global Enable Function The global enable function, controlled by the GLENx bits, is a feature that can reduce the number of write operations needed to set up the latch banks. This function is beneficial in systems that use a common configuration in multiple channels. The GLENx bit is present in bit 0 of latch banks 0 through 11 only. Its default value (1) enables the global update of the latch bank's contents. Setting the GLENx bit to 0 disables this functionality. Document #: 38-02102 Rev. *C Page 13 of 27 [+] Feedback CYV15G0404RB Latch Banks 12, 13, and 14 load values in the related latch banks in globally. A write operation to latch bank 12 performs a global write to latch banks 0, 3, 6, and 9, depending on the value of GLENx in these latch banks; latch bank 13 performs a global write to latch banks 1, 4, 7, and 10; and latch bank 14 performs a global write to latch banks 2, 5, 8, and 11. The GLENx bit cannot be modified by a global write operation. Force Global Enable Function FGLENx forces the global update of the target latch banks, but does not change the contents of the GLENx bits. If FGLENx = 1 for the associated global channel, FGLENx forces the global update of the target latch banks. Mask Function An additional latch bank (15) is a global mask vector that controls the update of the configuration latch banks on a bit-by-bit basis. A logic 1 in a bit location enables the update of that same location of the target latch bank(s), whereas a logic 0 disables it. The reset value of this latch bank is FFh, thereby making its use optional by default. The mask latch bank is not maskable. The bit 0 value of the mask latch bank does not affect the FGLEN functionality. Latch Types There are two types of latch banks: static (S) and dynamic (D). Each channel is configured by two static and one dynamic latch banks. The S type contains those settings that normally do not change for a given application, whereas the D type controls the settings that might change during the application's lifetime. The first and second rows of each channel (address numbers 0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The third row of latches for each channel (address numbers 2, 5, 8, and 11) are the dynamic control latches that are associated with enabling dynamic functions within the device. Latch Bank 14 is also useful for those users that do not need the latch based programmable feature of the device. This latch bank is used in those applications that do not need to modify the default value of the static latch banks, and that can afford global (that is, not independent) control of the dynamic signals. In this case, this feature becomes available when ADDR[3:0] is unchanged with a value of "1110" and WREN is asserted. The signals present in DATA[7:0] effectively become global control pins, and for the latch banks 2, 5, 8, and 11. Static Latch Values There are some latches in the table that have a static value (that is, 1, 0, or X). The latches that have a `1' or `0' must be configured with their corresponding value each time that their associated latch bank is configured. The latches that have an `X' are don't cares and can be configured with any value Table 3. Device Configuration and Control Latch Descriptions Name RXRATEA RXRATEB RXRATEC RXRATED Signal Description Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx selects the rate of the RXCLKx clock output. When RXRATEx = 1, the RXCLKx clock outputs are complementary clocks that follow the recovered clock operating at half the character rate. Data for the associated receive channels must latch alternately on the rising edge of RXCLKx+ and RXCLKx-. When RXRATEx = 0, the RXCLKx clock outputs are complementary clocks that follow the recovered clock operating at the character rate. Data for the associated receive channels must latch on the rising edge of RXCLKx+ or falling edge of RXCLKx-. Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the INx1 Primary Differential Serial Data Inputs. When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled. When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV. When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV. When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV. Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the INx2 Secondary Differential Serial Data Inputs. When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV. When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV. When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV. Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx selects the clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0, the associated TRGCLKx input is not multiplied before it is passed to the CDR PLL. When TRGRATEx = 1, the TRGCLKx input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and SPDSELx = LOW is an invalid state and this combination is reserved. SDASEL1A[1:0] SDASEL1B[1:0] SDASEL1C[1:0] SDASEL1D[1:0] SDASEL2A[1:0] SDASEL2B[1:0] SDASEL2C[1:0] SDASEL2D[1:0] TRGRATEA TRGRATEB TRGRATEC TRGRATED Document #: 38-02102 Rev. *C Page 14 of 27 [+] Feedback CYV15G0404RB Table 3. Device Configuration and Control Latch Descriptions (continued) Name RXPLLPDA RXPLLPDB RXPLLPDC RXPLLPDD RXBISTA[1:0] RXBISTB[1:0] RXBISTC[1:0] RXBISTD[1:0] Signal Description Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects whether the associated receive channel is enabled or powered down. RXPLLPDx = 0 powers down the associated receive PLL and analog circuitry. RXPLLPDx = 1 enables the associated receive PLL and analog circuitry. Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch = 11. For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11). RXBISTx[1:0] selects whether receive BIST is disabled or enabled and sets the associated channel for SMPTE data reception. RXBISTx[1:0] = 01 disables the receiver BIST function and sets the associated channel to receive SMPTE data. RXBISTx[1:0] = 10 enables the receive BIST function and sets the associated channel to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states. Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the ROE2x latch = 0. ROE2x selects whether the ROUT2 secondary differential output drivers are enabled or disabled. ROE2x = 1 enables the associated serial data output driver, allowing data to be transmitted from the transmit shifter. ROE2x = 0 disables the associated serial data output driver. When the configuration interface disables a driver, the driver internally powers down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel also powers down. A device reset (RESET sampled LOW) disables all output drivers. Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1x latch = 0. ROE1x selects whether the ROUT1 primary differential output drivers are enabled or disabled. ROE1x = 1 enables the associated serial data output driver, allowing data to be transmitted from the transmit shifter. ROE1x = 0 disables the associated serial data output driver. When the configuration interface disables a driver, the driver internally powers down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel also powers down. A device reset (RESET sampled LOW) disables all output drivers. Global Enable. The initialization value of the GLENx latch = 1. The GLENx reconfigures several channels simultaneously in applications where several channels may have the same configuration. When GLENx = 1 for a given address, that address can participate in a global configuration. When GLENx = 0 for a given address, that address cannot participate in a global configuration. Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global channel, FGLEN forces the global update of the target latch banks. permits it. [This is an optional step if the default settings match the desired configuration.] 3. Set the dynamic bank of latches for the target channel. Enable the Receive PLLs and set each channel for SMPTE data reception (RXBISTx[1:0] = 01) or BIST data reception (RXBISTx[1:0] = 10). You can perform this step using a global operation, if the application permits it. [Required step.] ROE2A ROE2B ROE2C ROE2D ROE1A ROE1B ROE1C ROE1D GLEN[11..0] FGLEN[2..0] Device Configuration Strategy Follow these steps to load the configuration latches on each channel: 1. Pulse RESET Low after device power up. This operation resets all four channels. Initialize the JTAG state machine to its reset state, as detailed in "JTAG Support" on page 17. 2. Set the static latch banks for the target channel. You can perform this step using a global operation, if the application Document #: 38-02102 Rev. *C Page 15 of 27 [+] Feedback CYV15G0404RB Table 4. Device Control Latch Configuration Table ADDR Channel Type 0 (0000b) 1 (0001b) 2 (0010b) 3 (0011b) 4 (0100b) 5 (0101b) 6 (0110b) 7 (0111b) 8 (1000b) 9 (1001b) 10 (1010b) 11 (1011b) A A A B B B C C C D D D S S D S S D S S D S S D S S D D DATA7 1 SDASEL2A[1] RXBISTA[1] 1 SDASEL2B[1] RXBISTB[1] 1 SDASEL2C[1] RXBISTC[1] 1 SDASEL2D[1] RXBISTD[1] 1 DATA6 0 SDASEL2A[0] RXPLLPDA 0 SDASEL2B[0] RXPLLPDB 0 SDASEL2C[0] RXPLLPDC 0 SDASEL2D[0] RXPLLPDD 0 DATA5 X SDASEL1A[1] RXBISTA[0] X SDASEL1B[1] RXBISTB[0] X SDASEL1C[1] RXBISTC[0] X SDASEL1D[1] RXBISTD[0] X DATA4 X SDASEL1A[0] X X SDASEL1B[0] X X SDASEL1C[0] X X SDASEL1D[0] X X DATA3 0 X ROE2A 0 X ROE2B 0 X ROE2C 0 X ROE2D 0 X ROE2GL D3 DATA2 0 X ROE1A 0 X ROE1B 0 X ROE1C 0 X ROE1D 0 X ROE1GL D2 DATA1 RXRATEA TRGRATEA X RXRATEB TRGRATEB X RXRATEC TRGRATEC X RXRATED TRGRATED X RXRATEGL TRGRATEGL X D1 DATA0 GLEN0 GLEN1 GLEN2 GLEN3 GLEN4 GLEN5 GLEN6 GLEN7 GLEN8 GLEN9 GLEN10 GLEN11 FGLEN0 FGLEN1 FGLEN2 D0 Reset Value 10111111 10101101 10110011 10111111 10101101 10110011 10111111 10101101 10110011 10111111 10101101 10110011 N/A N/A N/A 11111111 12 GLOBAL (1100b) 13 GLOBAL (1101b) 14 GLOBAL (1110b) 15 (1111b) MASK SDASEL2GL[1] SDASEL2GL[0] SDASEL1GL[1] SDASEL1GL[0] RXBISTGL[1] D7 RXPLLPDGL D6 RXBISTGL[0] D5 X D4 Document #: 38-02102 Rev. *C Page 16 of 27 [+] Feedback CYV15G0404RB JTAG Support The CYV15G0404RB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan and bypass are supported. This capability is present only on the LVTTL inputs and outputs and the TRGCLKx clock input. The high-speed serial inputs and outputs are not part of the JTAG test chain. To ensure valid device operation after power-up (including non-JTAG operation), the JTAG state machine must also be initialized to a reset state. This must be done in addition to the device reset (using RESET). Initialize the JTAG state machine using TRST (assert it LOW and deassert it or leave it asserted), or by asserting TMS HIGH for at least 5 consecutive TCLK cycles. This is necessary in order to ensure that the Table 5. Receive BIST Status Bits {BISTSTx, RXDx[0], RXDx[1]} 000, 001 010 011 100 101 110 111 JTAG controller does not enter any of the test modes after device power-up. In this JTAG reset state, the rest of the device will operate normally. Note The order of device reset (using RESET) and JTAG initialization does not matter. 3-Level Select Inputs Each 3-Level select input reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11 respectively JTAG ID The JTAG device ID for the CYV15G0404RB is `0C811069'x. Description Receive BIST Status (Receive BIST = Enabled) BIST Data Compare. Character compared correctly. BIST Last Good. Last Character of BIST sequence detected and valid. Reserved. BIST Last Bad. Last Character of BIST sequence detected invalid. BIST Start. Receive BIST is enabled on this channel, but character compares have not yet commenced. This also indicates a PLL Out of Lock condition. BIST Error. While comparing characters, a mismatch was found in one or more of the character bits. BIST Wait. The receiver is comparing characters, but has not yet found the start of BIST character to enable the LFSR. Document #: 38-02102 Rev. *C Page 17 of 27 [+] Feedback CYV15G0404RB Figure 2. Receive BIST State Machine Monitor Data Received Receive BIST {BISTSTx, RXDx[0], Detected LOW RXDx[1]} = BIST_START (101) RX PLL Out of Lock {BISTSTx, RXDx[0], RXDx[1]} = BIST_WAIT (111) No Start of BIST Detected Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) Compare Next Character Mismatch Yes Auto-Abort Condition Match {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) No End-of-BIST State End-of-BIST State No Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_LAST_BAD (100) Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_LAST_GOOD (010) No, {BISTSTx, RXDx[0], RXDx[1]} = BIST_ERROR (110) Document #: 38-02102 Rev. *C Page 18 of 27 [+] Feedback CYV15G0404RB Maximum Ratings Excedding maximum ratings may shorten the device life. User guidelines are not tested Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +3.8V DC Voltage Applied to LVTTL Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Output Current into LVTTL Outputs (LOW)..................60 mA DC Input Voltage....................................-0.5V to VCC + 0.5V Static Discharge Voltage.......................................... > 2000 V (MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA Power Up Requirements The CYV15G0404RB requires one power supply. The voltage on any input or I/O pin cannot exceed the power pin during power up. Operating Range Range Commercial Ambient Temperature 0C to +70C VCC +3.3V 5% CYV15G0404RB DC Electrical Characteristics Parameter LVTTL-compatible Outputs VOHT VOLT IOST IOZL VIHT VILT IIHT IILT IIHPDT IILPUT VDIFF[7] VIHHP VILLP VCOMREF VIHH VIMM VILL IIHH IIMM IILL [8] Description Output HIGH Voltage Output LOW Voltage Output Short Circuit Current High-Z Output Leakage Current Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Test Conditions IOH = -4 mA, VCC = Min. IOL = 4 mA, VCC = Min. VOUT = 0V[6], VCC = 3.3V Min 2.4 Max Unit V 0.4 -20 -20 2.0 -0.5 -100 20 VCC + 0.3 0.8 1.5 +40 -1.5 -40 +200 -200 400 1.2 0.0 1.0 VCC VCC VCC/2 VCC - 1.2V VCC 0.53 * VCC 0.13 * VCC 200 -50 50 -200 V mA A V V mA A mA A A A mV V V V V V V A A A VOUT = 0V, VCC LVTTL-compatible Inputs TRGCLKx Input, VIN = VCC Other Inputs, VIN = VCC TRGCLKx Input, VIN = 0.0V Other Inputs, VIN = 0.0V Input HIGH Current with Internal Pull Down VIN = VCC Input LOW Current with Internal Pull Up Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW voltage Common Mode Range Three-Level Input HIGH Voltage Three-Level Input MID Voltage Three-Level Input LOW Voltage Input HIGH Current Input MID current Input LOW current Min. VCC Max. Min. VCC Max. Min. VCC Max. VIN = VCC VIN = VCC/2 VIN = GND VIN = 0.0V LVDIFF Inputs: TRGCLKx 3-Level Inputs 0.87 * VCC 0.47 * VCC 0.0 Notes 6. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 7. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the true (+) input is more positive than the complement (-) input. A logic-0 exists when the complement (-) input is more positive than true (+) input. 8. The common mode range defines the allowable range of TRGCLKx+ and TRGCLKx- when TRGCLKx+ = TRGCLKx-. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. Document #: 38-02102 Rev. *C Page 19 of 27 [+] Feedback CYV15G0404RB CYV15G0404RB DC Electrical Characteristics (continued) Parameter VOHC VOLC VODIF Description Output HIGH Voltage (VCC Referenced) Output LOW Voltage (VCC Referenced) Output Differential Voltage |(OUT+) - (OUT-)| Test Conditions 100 differential load 150 differential load 100 differential load 150 differential load 100 differential load 150 differential load Min VCC - 0.5 VCC - 0.5 VCC - 1.4 VCC - 1.4 450 560 100 VCC - 2.0 VIN = VIHE Max. VIN = VILE Min. ((VCC - 2.0V)+0.5)min, (VCC - 0.5V) max. TRGCLKx = Commercial MAX Industrial TRGCLKx = Commercial 125 MHz Industrial -700 +1.25 Typ 910 900 +3.1 Max 1270 1320 1270 1320 mA mA mA mA 1350 Max VCC - 0.2 VCC - 0.2 VCC - 0.7 VCC - 0.7 900 1000 1200 VCC Unit V V V V mV mV mV V V A A V Differential CML Serial Outputs: ROUTA1, ROUTA2, ROUTB1, ROUTB2, ROUTC1, ROUTC2, ROUTD1, ROUTD2 Differential Serial Line Receiver Inputs: INA1, INA2, INB1, INB2, INC1, INC2, IND1, IND2 VDIFFs[7] VIHE VILE IIHE IILE VICOM [9] Input Differential Voltage |(IN+) - (IN-)| Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current Common Mode input range Power Supply ICC [10,11] Max Power Supply Current Typical Power Supply Current ICC [10,11] AC Test Loads and Waveforms 3.3V R1 R1 = 590 R2 = 435 CL CL 7 pF (Includes fixture and probe capacitance) RL = 100 (Includes fixture and probe capacitance) RL R2 [12] (b) CML Output Test Load [12] (a) LVTTL Output Test Load 3.0V Vth = 1.4V GND 1 ns 2.0V 0.8V 2.0V 0.8V VIHE Vth = 1.4V VILE 1 ns 20% VIHE 80% VILE 80% 20% 270 ps 270 ps (c) LVTTL Input Test Waveform [13] (d) CML/LVPECL Input Test Waveform Notes 9. The common mode range defines the allowable range of INPUT+ and INPUT- when INPUT+ = INPUT-. This marks the zero crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. 10. Maximum ICC is measured with VCC = MAX, TA = 25C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and outputs unloaded. 11. Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25C, with all channels enabled and one Serial Line Driver for each transmit channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded. 12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage. Document #: 38-02102 Rev. *C Page 20 of 27 [+] Feedback CYV15G0404RB CYV15G0404RB AC Electrical Characteristics Parameter fRS tRXCLKP tRXCLKD tRXCLKR [14] tRXCLKF tRXDv- [14] [18] Description RXCLKx Clock Output Frequency RXCLKx Period = 1/fRS RXCLKx Duty Cycle Centered at 50% (Full Rate and Half Rate) RXCLKx Rise Time RXCLKx Fall Time Status and Data Valid Time to RXCLKx (RXRATEx = 0) (Full Rate) Status and Data Valid Time to RXCLKx (RXRATEx = 1) (Half Rate) Status and Data Valid Time to RXCLKx (RXRATEx = 0) Status and Data Valid Time to RXCLKx (RXRATEx = 1) RECLKOx Clock Frequency RECLKOx Period = 1/fROS RECLKOx Duty Cycle centered at 60% HIGH time TRGCLKx Clock Frequency TRGCLKx Period = 1/fREF TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate) TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate) TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate) TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate) TRGCLKx Duty Cycle TRGCLKx Rise Time (20%-80%) TRGCLKx Fall Time (20%-80%) TRGCLKx Frequency Referenced to Received Clock Frequency Bus Configuration Data Hold Bus Configuration Data Setup Bus Configuration WREN Pulse Width JTAG Test Clock Frequency JTAG Test Clock Period Min 9.75 6.66 -1.0 0.3 0.3 5UI-2.0 5UI-1.3 5UI-2.6 19.5 6.66 -1.9 19.5 6.6 5.9 2.9 2.9 [14] [19] [19] Max 150 102.56 +1.0 1.2 1.2 Unit MHz ns ns ns ns ns ns ns ns CYV15G0404RB Receiver LVTTL Switching Characteristics Over the Operating Range tRXDv+[18] fROS tRECLKO tRECLKOD fTRG TRGCLK 5UI-1.8[19] [19] 150 51.28 0 150 51.28 MHz ns ns MHz ns ns ns ns ns CYV15G0404RB TRGCLKx Switching Characteristics Over the Operating Range tTRGH tTRGL tTRGD[20] tTRGR [14, 15, 16, 17] 5.9 [14] 30 70 2 2 % ns ns % ns ns ns tTRGF[14, 15, 16, 17] tTRGRX[21] tDATAH tDATAS tWRENP fTCLK tTCLK -0.15 0 10 10 +0.15 CYV15G0404RB Bus Configuration Write Timing Characteristics Over the Operating Range CYV15G0404RB JTAG Test Clock Characteristics Over the Operating Range 20 50 MHz ns Notes 14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 15. The ratio of rise time to falling time must not vary by greater than 2:1. 16. For a given operating frequency, neither rise nor fall specification can be greater than 20% of the clock cycle period or the data sheet maximum time. 17. All transmit AC timing parameters measured with 1ns typical rise time and fall time. 18. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads. 19. Receiver UI (Unit Interval) is calculated as 1/(fTRG * 20) (when TRGRATEx = 1) or 1/(fTRG * 10) (when TRGRATEx = 0). In an operating link this is equivalent to tB. 20. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the TRGCLKx duty cycle cannot be as large as 30%-70%. 21. TRGCLKx has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. TRGCLKx must be within 1500 PPM (0.15%) of the transmitter PLL reference (REFCLKx) frequency. Although transmitting to a HOTLink II receiver channel necessitates the frequency difference between the transmitter and receiver reference clocks to be within 1500-PPM, the stability of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. Document #: 38-02102 Rev. *C Page 21 of 27 [+] Feedback CYV15G0404RB CYV15G0404RB AC Electrical Characteristics (continued) Parameter tRST Parameter tB tRISE[14] Bit Time CML Output Rise Time 20-80% (CML Test Load) SPDSELx = HIGH SPDSELx = MID SPDSELx =LOW tFALL [14] Description Device RESET Pulse Width Description Condition Min 30 Min. 5128 50 100 180 50 100 180 Max Unit ns CYV15G0404RB Device RESET Characteristics Over the Operating Range CYV15G0404RB Reclocker Serial Output Characteristics Over the Operating Range Max. 660 270 500 1000 270 500 1000 Unit ps ps ps ps ps ps ps CML Output Fall Time 80-20% (CML Test Load) SPDSELx = HIGH SPDSELx = MID SPDSELx =LOW PLL Characteristics Parameter tJRGENSD[14, 22] tJRGENHD[14, 22] tRXLOCK tRXUNLOCK Description Reclocker Jitter Generation - SD Data Rate Reclocker Jitter Generation - HD Data Rate Receive PLL Lock to Input Data Stream (cold start) Receive PLL Lock to Input Data Stream Receive PLL Unlock Rate Condition TRGCLKx = 27 MHz TRGCLKx = 148.5 MHz Min Typ 133 107 376k 376k 46 Max Unit ps ps UI UI UI CYV15G0404RB Reclocker Output PLL Characteristics CYV15G0404RB Receive PLL Characteristics Over the Operating Range Capacitance[14] Parameter CINTTL CINPECL Description TTL Input Capacitance PECL input Capacitance Test Conditions TA = 25C, f0 = 1 MHz, VCC = 3.3V TA = 25C, f0 = 1 MHz, VCC = 3.3V Max 7 4 Unit pF pF Note 22. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide bandwidth digital sampling oscilloscope. The measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx of the transmit channel. Document #: 38-02102 Rev. *C Page 22 of 27 [+] Feedback CYV15G0404RB Switching Waveforms for the CYV15G0404RB HOTLink II Receiver Receive Interface Read Timing RXRATEx = 0 RXCLKx+ tRXCLKP RXCLKx- tRXDV- RXDx[9:0] tRXDV+ Receive Interface Read Timing RXRATEx = 1 RXCLKx+ tRXCLKP RXCLKx- tRXDV- RXDx[9:0] tRXDV+ CYV15G0404RB HOTLink II Bus Configuration Switching Waveforms Bus Configuration Write Timing ADDR[3:0] DATA[7:0] tWRENP WREN tDATAS tDATAH Document #: 38-02102 Rev. *C Page 23 of 27 [+] Feedback CYV15G0404RB Table 6. Package Coordinate Signal Allocation Ball ID A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Signal Name INC1- ROUTC1- INC2- ROUTC2- VCC IND1- ROUTD1- GND IND2- ROUTD2- INA1- ROUTA1- GND INA2- ROUTA2- VCC INB1- ROUTB1- INB2- ROUTB2- INC1+ ROUTC1+ INC2+ ROUTC2+ VCC IND1+ ROUTD1+ GND IND2+ ROUTD2+ INA1+ ROUTA1+ GND INA2+ ROUTA2+ VCC INB1+ ROUTB1+ INB2+ Signal Type CML IN CML OUT CML IN CML OUT POWER CML IN CML OUT GROUND CML IN CML OUT CML IN CML OUT GROUND CML IN CML OUT POWER CML IN CML OUT CML IN CML OUT CML IN CML OUT CML IN CML OUT POWER CML IN CML OUT GROUND CML IN CML OUT CML IN CML OUT GROUND CML IN CML OUT POWER CML IN CML OUT CML IN Ball ID C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 E03 E04 E17 Signal Name ULCC GND DATA[7] DATA[5] DATA[3] DATA[1] GND VCC SPDSELD VCC LDTDEN TRST GND TDO TCLK RESET INSELD INSELA VCC ULCA SPDSELC GND DATA[6] DATA[4] DATA[2] DATA[0] GND GND ULCB VCC NC VCC SCANEN2 TMEN3 VCC VCC VCC VCC VCC Signal Type LVTTL IN PU GROUND LVTTL IN PU LVTTL IN PU LVTTL IN PU LVTTL IN PU GROUND POWER 3-LEVEL SEL POWER LVTTL IN PU LVTTL IN PU GROUND LVTTL 3-S OUT LVTTL IN PD LVTTL IN PU LVTTL IN LVTTL IN POWER LVTTL IN PU 3-LEVEL SEL GROUND LVTTL IN PU LVTTL IN PU LVTTL IN PU LVTTL IN PU GROUND GROUND LVTTL IN PU POWER NO CONNECT POWER LVTTL IN PD LVTTL IN PD POWER POWER POWER POWER POWER Ball ID F17 F18 F19 F20 G01 G02 G03 G04 G17 G18 G19 G20 H01 H02 H03 H04 H17 H18 H19 H20 J01 J02 J03 J04 J17 J18 J19 J20 K01 K02 K03 K04 K17 K18 K19 K20 L01 L02 L03 Signal Name VCC RXDB[0] RECLKOB RXDB[1] GND WREN GND GND SPDSELB NC SPDSELA RXDB[3] GND GND GND GND GND GND GND GND GND GND GND GND BISTSTB RXDB[2] RXDB[7] RXDB[4] RXDC[4] TRGCLKC- GND GND RXDB[5] RXDB[6] RXDB[9] LFIB RXDC[5] TRGCLKC+ LFIC Signal Type POWER LVTTL OUT LVTTL OUT LVTTL OUT GROUND LVTTL IN PU GROUND GROUND 3-LEVEL SEL NO CONNECT 3-LEVEL SEL LVTTL OUT GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT PECL IN GROUND GROUND LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT PECL IN LVTTL OUT Document #: 38-02102 Rev. *C Page 24 of 27 [+] Feedback CYV15G0404RB Table 6. Package Coordinate Signal Allocation (continued) Ball ID B20 C01 C02 C03 C04 C05 C06 M03 M04 M17 M18 M19 M20 N01 N02 N03 N04 N17 N18 N19 N20 P01 P02 P03 P04 P17 P18 P19 P20 R01 R02 R03 R04 R17 R18 R19 R20 T01 T02 Signal Name ROUTB2+ TDI TMS INSELC INSELB VCC ULCD VCC REPDOC TRGCLKB+ TRGCLKB- REPDOB GND GND GND GND GND GND GND GND GND RXDC[3] RXDC[2] RXDC[1] RXDC[0] GND GND GND GND BISTSTC RECLKOC RXCLKC+ RXCLKC- VCC VCC VCC VCC VCC VCC Signal Type CML OUT LVTTL IN PU LVTTL IN PU LVTTL IN LVTTL IN POWER LVTTL IN PU POWER LVTTL OUT PECL IN PECL IN LVTTL OUT GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT GROUND GROUND GROUND GROUND LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT POWER POWER POWER POWER POWER POWER Ball ID E18 E19 E20 F01 F02 F03 F04 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 Signal Name VCC VCC VCC RXDC[8] RXDC[9] VCC VCC VCC VCC VCC RXDD[4] RXDD[3] GND GND ADDR [0] TRGCLKD- GND GND GND VCC VCC RXDA[4] VCC BISTSTA RXDA[0] VCC VCC VCC RXDD[8] VCC RXDD[5] RXDD[1] GND BISTSTD ADDR [2] TRGCLKD+ RECLKOA GND GND Signal Type POWER POWER POWER LVTTL OUT LVTTL OUT POWER POWER POWER POWER POWER LVTTL OUT LVTTL OUT GROUND GROUND LVTTL IN PU PECL IN GROUND GROUND GROUND POWER POWER LVTTL OUT POWER LVTTL OUT LVTTL OUT POWER POWER POWER LVTTL OUT POWER LVTTL OUT LVTTL OUT GROUND LVTTL OUT LVTTL IN PU PECL IN LVTTL OUT GROUND GROUND Ball ID L04 L17 L18 L19 L20 M01 M02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Signal Name GND RXDB[8] RXCLKB+ RXCLKB- GND RXDC[6] RXDC[7] LFID RXCLKD- VCC RXDD[6] RXDD[0] GND ADDR [3] ADDR [1] RXCLKA+ REPDOA GND GND VCC VCC LFIA TRGCLKA+ RXDA[6] RXDA[3] VCC VCC RXDD[9] RXCLKD+ VCC RXDD[7] RXDD[2] GND RECLKOD NC GND RXCLKA- GND GND Signal Type GROUND LVTTL OUT LVTTL OUT LVTTL OUT GROUND LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT POWER LVTTL OUT LVTTL OUT GROUND LVTTL IN PU LVTTL IN PU LVTTL OUT LVTTL OUT GROUND GROUND POWER POWER LVTTL OUT PECL IN LVTTL OUT LVTTL OUT POWER POWER LVTTL OUT LVTTL OUT POWER LVTTL OUT LVTTL OUT GROUND LVTTL OUT NO CONNECT GROUND LVTTL OUT GROUND GROUND Document #: 38-02102 Rev. *C Page 25 of 27 [+] Feedback CYV15G0404RB Table 6. Package Coordinate Signal Allocation (continued) Ball ID T03 T04 T17 T18 T19 T20 U01 U02 Signal Name VCC VCC VCC VCC VCC VCC VCC VCC Signal Type POWER POWER POWER POWER POWER POWER POWER POWER Ball ID V15 V16 V17 V18 V19 V20 W01 W02 Signal Name VCC VCC RXDA[9] RXDA[5] RXDA[2] RXDA[1] VCC VCC Signal Type POWER POWER LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT POWER POWER Ball ID Y15 Y16 Y17 Y18 Y19 Y20 Signal Name VCC VCC REPDOD TRGCLKA- RXDA[8] RXDA[7] Signal Type POWER POWER LVTTL OUT PECL IN LVTTL OUT LVTTL OUT Ordering Information Speed Standard Standard Ordering Code CYV15G0404RB-BGC CYV15G0404RB-BGXC Package Name BL256 BL256 Package Type 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Operating Range Commercial Commercial Package Diagram Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256 TOP VIEW 27.000.13 A1 CORNER I.D. 0.20(4X) A O0.15 M C O0.30 M C O0.750.15(256X) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y BOTTOM VIEW (BALL SIDE) A B 24.13 A1 CORNER I.D. R 2.5 Max (4X) 27.000.13 12.065 1.27 24.13 A B 1.570.175 0.97 REF. 0.15 C 0.50 MIN. A 0.600.10 C 26 TYP. 0.15 C SEATING PLANE 0.20 MIN TOP OF MOLD COMPOUND TO TOP OF BALLS SIDE VIEW SECTION A-A 51-85123-*E HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-02102 Rev. *C Page 26 of 27 (c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CYV15G0404RB Document History Page Document Title: CYV15G0404RB Independent Clock Quad HOTLink IITM Deserializing Reclocker Document Number: 38-02102 REV. ** *A *B *C ECN NO. 246850 338721 384307 789283 ISSUE DATE See ECN See ECN See ECN See ECN ORIG. OF CHANGE FRE SUA AGT KKVTMP New Data Sheet Added Pb-Free package option availability Revised setup and hold times (tRXDv-, tRXDv+) Clarification to the need and procedure to initialize the JTAG controller (during test and non-test mode) to ensure valid device power-up. No changes have been made to the device specifications or characterestics. DESCRIPTION OF CHANGE Document #: 38-02102 Rev. *C Page 27 of 27 [+] Feedback |
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